SH7760 Datasheet, PDF (249/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(4) IRQ Interrupts
• Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit
in SR is 0 (accepted at instruction boundary).
• Transition address: VBR + H'0000 0600
• Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits
are set to 1 in SR, and a branch is made to VBR + H'0600. The IRQ interrupt levels should be
set as values between B'0000 and B'1111 in the interrupt priority level setting register 00
(INTPRI00) in the interrupt controller. For details, see section 9, Interrupt Controller (INTC).
IRQ()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'0000 0800 ~ H'0000 0860;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0600;
}
Rev. 1.0, 02/03, page 199 of 1294