SH7760 Datasheet, PDF (445/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
0
UTF
0
R/W USB Transfer End Interrupt Flag
0: An interrupt has not occurred.
[Clearing condition]
When 0 is written to UTF after reading UTF = 1
1: An interrupt has occurred.
11.3.10 DMA Audio Source Address Register (DMAATXSAR)
DMAATXSAR is a 32-bit readable/writable register that specifies the source start address of a
DMA transfer from synchronous DRAM to the HAC or SSI codec. DMAATXSAR0 corresponds
to HAC(0) or SSI(0) and DMAATXSAR1 corresponds to HAC(1) or SSI(1). During a DMA
transfer, the register value is not modified.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
11.3.11 DMA Audio Destination Address Register (DMAARXDAR)
DMAARXDAR is a 32-bit readable/writable register that specifies the destination start address of
a DMA transfer from the HAC or SSI codec to synchronous DRAM. DMAARXDAR0
corresponds to HAC(0) or SSI(0) and DMAARXDAR1 corresponds to HAC(1) or SSI(1). During
a DMA transfer, the register value is not modified.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Rev. 1.0, 02/03, page 395 of 1294