SH7760 Datasheet, PDF (603/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.3.3 Transmit Shift Register (SCTSR)
SCTSR is the register used to transmit serial data.
To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to
SCTSR, then sends the data to the SCIF_TXD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCFTDR
to SCTSR, and transmission started, automatically.
SCTSR cannot be directly read from and written to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
17.3.4 Transmit FIFO Data Register (SCFTDR)
SCFTDR is an 8-bit FIFO register of 128 stages that stores data for serial transmission.
If SCTSR is empty when transmit data has been written to SCFTDR, the SCIF transfers the
transmit data written in SCFTDR to SCTSR and starts serial transmission.
SCFTDR is a write-only register, and cannot be read by the CPU.
The next data cannot be written when SCFTDR is filled with 128 bytes of transmit data. Data
written in this case is ignored.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: W W W W W W W W
Rev. 1.0, 02/03, page 553 of 1294