SH7760 Datasheet, PDF (1108/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

30.3.17 LCDC Power Management Mode Register (LDPMMR)
LDPMMR controls the power supply circuit that provides power to the LCD module. The usage
of two types of power-supply control pins, VCPWC and VEPWC, and turning on or off the power
supply function are selected.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
ONC3 ONC2 ONC1 ONC0 OFFD3 OFFD2 OFFD1 OFFD0 - VCPE VEPE DONE -
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R
2
1
0
- LPS1 LPS0
0
0
0
R
R
R
Bit Bit Name Initial Value R/W Description
15
ONC3
0
14
ONC2
0
13
ONC1
0
12
ONC0
0
R/W LCDC Power-On Sequence Period
R/W _{Sets the period from VEPWC assertion to}
R/W _{LCD_DON assertion in the power-on sequence of}
R/W _{the LCD module in frame units.}
Specify a value of (the period) −1.
This period is the (c) period in figures 30.4 to 30.7,
Power-Supply Control Sequence and States of the
LCD Module. For details on setting this register, see
table 30.5, Available Power-Supply Control-
Sequence Periods at Typical Frame Rates. (The
setting method is common for ONA, ONB, OFFD,
OFFE, and OFFF.)
11
OFFD3
0
10
OFFD2
0
9
OFFD1
0
8
OFFD0
0
R/W LCDC Power-Off Sequence Period
R/W _{Sets the period from LCD_DON negation to}
R/W _{VEPWC negation in the power-off sequence of the}
R/W _{LCD module in frame units.}
Specify a value of (the period) −1.
This period is the (d) period in figures 30.4 to 30.7,
Power-Supply Control Sequence and States of the
LCD Module.
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
VCPE
0
R/W VCPWC Pin Enable
Sets whether or not to enable a power-supply
control sequence using the VCPWC pin.
0: Disabled: VCPWC pin output is masked and
fixed low
1: Enabled: VCPWC pin output is asserted and
negated according to the power-on or power-off
sequence
Rev. 1.0, 02/03, page 1058 of 1294