SH7760 Datasheet, PDF (397/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
RD/FRAME
D31−D0
CSn
RD/WR
Tm1 Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8
A
D1
D2
D3
D4
D5
D6
D7
D8
RDY
BS
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.50 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait,
32-Bit Bus Width, 32-Byte Data Transfer)
CKIO
RD/FRAME
D31−D0
CSn
RD/WR
Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3
A
D1
D2
D3
Tmd7 Tmd8w Tmd8
D7
D8
RDY
BS
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.51 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control,
32-Bit Bus Width, 32-Byte Data Transfer)
Rev. 1.0, 02/03, page 347 of 1294