SH7760 Datasheet, PDF (886/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

23.4 Operation
23.4.1 Operation Overview without DMA (FIFO Mode Disabled)
Figure 23.2 shows the flow of a transmit/receive operation procedure.
Start
Reset the system
Select master or slave
mode by setting the MASL bit
in SPSCR
Select required interrupts by
setting TFIE and ROIE bits in
SPSCR
Check if
TXBUFF is empty by
reading the TXFL bit
in SPSR
Yes
Write data to SPTBR
No
HSPI_TX data to/from slave
Yes
Another
transmit required?
No
End
Figure 23.2 Operational Flowchart
Depending on the settings of SPCR, the master transmits data to the slave on either the falling or
rising edge of HSPI_CLK and samples data from the slave on the opposite edge. The data transfer
between the master and slave completes when the transmit complete status flag (TXFN) in SPSR
is set to 1. This flag should be used to identify when an HSPI transfer event (byte transmitted and
byte received) has occurred, even in the case where the HSPI module is being used to receive data
only (null data being transmitted). By default data is transmitted MSB first, but LSB first is also
possible depending on how the LMSB bit in SPSCR is set.
During the transmit function the slave responds by sending data to the master synchronized with
the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the
shift register in the module and on completion of the transmit function, is transferred to SPRBR.
Rev. 1.0, 02/03, page 836 of 1294