SH7760 Datasheet, PDF (270/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.4.5 Interrupt Exception Handling and Priority
Table 9.7 lists the codes for the interrupt event register (INTEVT), and the order of interrupt
priority.
Each interrupt source is assigned a unique INTEVT code. The start address of the exception
handling routine is common to each interrupt source. Therefore, to identify the interrupt source,
branching is performed at the start of the exception handling routine using the INTEVT value. For
instance, the INTEVT value is used as a branch offset .
The priority order of the peripheral modules is specified as desired by setting priority levels from
15 to 0 in IPRA to IPRD and INTPRI00 to INTPRI0C. The priority order of the peripheral
modules is set to 0 by a reset.
When the priorities for multiple interrupt sources are set to the same level and such interrupts are
generated simultaneously, they are handled according to the default priority order shown in table
9.7.
Updating of IPRA to IPRD and INTPRI00 to INTPRI0C should only be carried out when the BL
bit in SR is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt
priority level setting registers, then clear the BL bit to 0. This will secure the necessary timing
internally.
Rev. 1.0, 02/03, page 220 of 1294