SH7760 Datasheet, PDF (271/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 9.7 Interrupt Exception Handling Sources and Priority Order
Interrupt Source
INTEVT Interrupt Priority Relevant IPR Priority within Default
Code (Initial Value) (Bit Numbers) IPR Setting Unit Priority
NMI
H'1C0 16
—
—
High
IRL3 to IRL3 to IRL0 = 0 H'200 15
IRL0 _{IRL3 to IRL0 = 1 H'220 14}
—
—
—
—
IRL3 to IRL0 = 2 H'240 13
—
—
IRL3 to IRL0 = 3 H'260 12
—
—
IRL3 to IRL0 = 4 H'280 11
—
—
IRL3 to IRL0 = 5 H'2A0 10
—
—
IRL3 to IRL0 = 6 H'2C0 9
—
—
IRL3 to IRL0 = 7 H'2E0 8
—
—
IRL3 to IRL0 = 8 H'300 7
—
—
IRL3 to IRL0 = 9 H'320 6
—
—
IRL3 to IRL0 = A H'340 5
—
—
IRL3 to IRL0 = B H'360 4
—
—
IRL3 to IRL0 = C H'380 3
—
—
IRL3 to IRL0 = D H'3A0 2
—
—
IRL3 to IRL0 = E H'3C0 1
—
—
IRL IRL0
H'240 15 to 0 (13)
IPRD (15 to 12) —
IRL1
H'2A0 15 to 0 (10)
IPRD (11 to 8) —
IRL2
H'300 15 to 0 (7)
IPRD (7 to 4) —
IRL3
H'360 15 to 0 (4)
IPRD (3 to 0) —
H-UDI H-UDI
H'600 15 to 0 (0)
IPRC (3 to 0) —
GPIO GPIOI
H'620 15 to 0 (0)
IPRC (15 to 12) —
Low
Rev. 1.0, 02/03, page 221 of 1294