SH7760 Datasheet, PDF (951/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(1) Writing a codec register address to HACCSAR
Write a codec register address to HACCSAR twice with an interval of 100ns.
(2) Writing data to a codec register
After writing data to a codec register, verify the write data by reading this codec register. If the
write is unsuccessful, carry out writing again.
(3) Reading from a codec register
When HACTSR.CMDAMT is accidentally set to 1, a read access to the codec register is not
performed and therefore neither HACRSR.STARY nor HACRSR.STDRY is set to 1 to
indicate data reception. If HACRSR.STARY and HACRSR.STDRY stay 0 for a longer time
than expected in normal read operation, it should be regarded as timeout. Carry out reading
again.
For details of the initialization sequence, see 25.5.6, Initialization Sequence.
Rev. 1.0, 02/03, page 901 of 1294