SH7760 Datasheet, PDF (278/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.6 Interrupt Response Time
The time from interrupt request generation until interrupt exception handling is performed and
fetching of the first instruction of the exception handling routine is started (the interrupt response
time) is shown in table 9.8.
Table 9.8 Interrupt Response Time
Number of States
Item
Peripheral
NMI
IRL IRQ Modules
Time for priority decision and 1 Icyc + 4 Bcyc 1 Icyc + 7 Bcyc 1 Icyc + 2 Bcyc
SR mask bit comparison
Wait time until end of
sequence being executed by
CPU
S – 1 (≥ 0) ×
Icyc
S – 1 (≥ 0) ×
Icyc
S – 1 (≥ 0) ×
Icyc
Time from interrupt exception
handling (save of SR and PC)
until fetch of first instruction of
exception handling routine is
started
4 × Icyc
4 × Icyc
4 × Icyc
Response
time
Total
5 Icyc + 4 Bcyc 5 Icyc + 7 Bcyc 5 Icyc + 2 Bcyc
+ (S – 1) Icyc + (S – 1) Icyc + (S – 1) Icyc
Minimum
case
13 Icyc
19 Icyc
9 Icyc
Maximum
case
36 + S Icyc
60 + S Icyc
20 + S Icyc
Icyc : One cycle of internal clock supplied to CPU, etc.
Bcyc : One CKIO cycle
S : Number of instruction execution states
Notes
When Icyc:
Bcyc = 2:1
When Icyc:
Bcyc = 8:1
Rev. 1.0, 02/03, page 228 of 1294