SH7760 Datasheet, PDF (313/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
2
A0B2 1
1
A0B1 1
0
A0B0 1
R/W Area 0 Burst Pitch
R/W
These bits specify the number of wait cycles to be
R/W
inserted for the second and following data accesses in
burst transfer when area 0 is specified as burst ROM
area.
Inserted wait cycles
RDY pin
000: 0
Disabled
001: 1
Enabled
010: 2
Enabled
011: 3
Enabled
100: 4
Enabled
101: 5
Enabled
110: 6
Enabled
111: 7
Enabled
Notes: *1. External wait input is always ignored
*2. Inhibited in RAS down mode
Table 10.8 MPX Interface Setting
AnW2
AnW1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note: n = 0 to 6
AnW0
0
1
0
1
0
1
0
1
Description
Inserted Wait Cycles
1st Data
Read
Write
2nd Data
and After
1
0
0
1
1
0
2
2
0
3
3
0
1
0
1
1
1
1
2
2
1
3
3
1
RDY Pin
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Rev. 1.0, 02/03, page 263 of 1294