SH7760 Datasheet, PDF (137/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(e) Flow dependency
Zero-cycle latency
MOV R0,R1
ADD R2,R1
I
D EX NA S
I
D EX NA S
ADD R2,R1
MOV.L @R1,R1
next
1-cycle latency
I
D EX NA S
I
i
D EX MA S
I ...
1 stall cycle
The following instruction, ADD, is not
stalled when executed after an instruction
with zero-cycle latency, even if there is
dependency.
ADD and MOV.L are not executed in
parallel, since MOV.L references the result
of ADD as its load address.
MOV.L @R1,R1
ADD R0,R1
next
MOV.L @R1,R1
SHAD R1,R2
next
2-cycle latency
I
D EX MA S
I
D
EX NA S
I ... 1 stall cycle
Because MOV.L and ADD are not fetched
simultaneously in this example, ADD is
stalled for only 1 cycle even though the
latency of MOV.L is 2 cycles.
2-cycle latency
1-cycle increase
I
D EX MA S
Due to the flow dependency between the
I
D
d EX NA S ^{load and the SHAD/SHLD shift amount,}
I ...
2 stall cycles
the latency of the load is increased to 3
cycles.
FADD FR1,FR2
STS FPUL,R1
STS FPSCR,R2
FADD DR0,DR2
FMOV FR3,FR5
FMOV FR2,FR4
4-cycle latency for FPSCR
I
D F1 F2 FS
I
D EX NA S
I
D EX NA S
2 stall cycles
7-cycle latency for lower FR
8-cycle latency for upper FR
I
D F1 F2 FS
d F1 F2 FS
d F1 F2 FS
d F1 F2 FS
d
F1 F2 FS FR3 write
F1 F2 FS FR2 write
I
D EX NA S
I
D EX NA S
FLOAT FPUL,DR0
I
FMOV.S FR0,@-R15
I
FLDI1 FR3
I
FIPR FV0,FV4
I
FMOV @R1,XD14
I
FTRV XMTRX,FV0
I
3-cycle latency for upper/lower FR
D F1 F2 FS FR1 write
d
F1 F2 FS FR0 write
D
EX MA S
Zero-cycle latency
3-cycle increase
D EX NA S
D
d F0 F1 F2 FS
3 stall cycles
2-cycle latency
1-cycle increase
D EX MA S
D
d
3 stall cycles
F0 F1 F2
d F0 F1
d F0
d
FS
F2 FS
F1 F2 FS
F0 F1 F2 FS
Figure 5.3 Examples of Pipelined Execution (cont)
Rev. 1.0, 02/03, page 87 of 1294