SH7760 Datasheet, PDF (725/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

4. ICMCR=H’0000 0009 (set ESG) //ESG=1, MIE=1, MDBS=0. (At this point, the slave address
is output onto I²C bus.)
5. Wait for MAT, and clear ESG.
6. ICFSR=H’0000 0000 (Clear the flag.)
7. Wait for TDFE, and read the data received from ICRXD.
ICFSR=H’0000 0000 (clear the flag)
(Repeat)
If setting FSB to 1, wait for one bit period after setting RDF to 1 and read the data received
from ICRXD.
8. Set FSB to 1.
9. ICFSR=H’0000 0000 (Clear the flag.)
19.7 Usage Notes
19.7.1 Restriction 1
For a master transmitter in single buffer mode, the following restriction should be taken into
account.
There is a restriction on a write of the second and following bytes to ICTXD register and a set of
FSB to 1. Details are discussed it in the following paragraphs.
For details of master transmitter operation in single buffer mode, see 19.4.8, Master Transmitter
Operation (Single Buffer Mode). This section mainly describes flag manipulation in relation to the
restriction. Below shown are operational examples for transmission of one-byte, two-byte, and
three-byte data. When two or more bytes are transmitted, writing of the second and third bytes is
subject to the timing restriction. Meanwhile, single-byte data transmission has no timing
restriction. When transmitting three or more bytes, delay manipulation of the third byte
transmission will remove the timing restriction on writing of the succeeding transmit bytes.
(Transmission is stopped with the MDE flag being set to 1.)
(1) One-byte data transmission
Figure 19.11 shows an operational example of one-byte data transmission.
Write data 1 before clearing the MAT and MDE flags to 0 in (2) (for example, in initial setting
preceding the issue of start conditions.). Once the MDE flag is cleared, data transmission starts.
Set the FSB flag to 1 at the timing between (1) and (3) (for example, before the MAT and
MDE flags are cleared in (2)).
Rev. 1.0, 02/03, page 675 of 1294