SH7760 Datasheet, PDF (497/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.6 DMABRG Operation
The DMABRG has independent FIFOs (32-bit 16-stage) for the LCDC, HAC, SSI, and USB with
which it performs DMA transfers between the LCDC, HAC, SSI, and USB and synchronous
DRAM. The DMABRG transfers a maximum of 32-byte data in a single DMA transfer.
11.6.1 DMABRG Request
DMA transfer by the DMABRG is performed using DMAC channel 0. The independent FIFOs
(32-bit 16-stage) for the LCDC, HAC, SSI, and USB generate DMABRG requests. The LCDC,
HAC, SSI, and USB that are connected to the DMABRG can operate at the same time.
CHCR0*, SAR0, and DAR0 are automatically set according to the LCDC or DMABRG register
settings. CHCR0, SAR0, and DAR0 do not have to be set (rewritten) by the CPU.
Note: * If CHCR0.DE = 1 is set by the CPU, an address error may occur (DMAOR.AE = 1) and
the DMAC will stop operation. When using DMABRG requests, make sure the CPU
does not set CHCR0.DE = 1.
11.6.2 DMABRG Reset
The DMAC of this LSI suspends a DMA transfer when the following conditions are met.
(1) NMI interrupt occurred
(2) DMA address error occurred
When the DMAC suspends a DMA transfer by the above conditions while using the DMABRG
(LCDC, HAC, SSI, or USB), reset the DMABRG (CHCR.CHSET = 1), re-specify the DMAC
registers*, and then reactivate the DMAC.
Setting the BRGRST bit in DMAPCR to 1 resets the DMABRG. The reset is canceled by clearing
the BRGRST bit to 0. Resetting the DMABRG forcibly terminates DMA transfer for the HAC,
SSI, USB, or LCDC. In this case, a transfer end interrupt is not generated.
Resetting the DMABRG initializes the following registers to the state of a power-on reset.
• DMABRGCR
• DMAACR
• DMAUSAR
• DMAUDAR
• DMAURWSZ
• DMAUCR
Rev. 1.0, 02/03, page 447 of 1294