SH7760 Datasheet, PDF (10/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
ITLB Address Array ............................................................................................ 131
ITLB Data Array 1............................................................................................... 132
ITLB Data Array 2............................................................................................... 133
UTLB Address Array........................................................................................... 133
UTLB Data Array 1 ............................................................................................. 135
UTLB Data Array 2 ............................................................................................. 136
Section 7 Caches................................................................................................137
7.1 Features............................................................................................................................. 137
7.2 Register Descriptions ........................................................................................................ 141
7.2.1 Cache Control Register (CCR) ............................................................................ 142
7.2.2 Queue Address Control Register 0 (QACR0) ...................................................... 144
7.2.3 Queue Address Control Register 1 (QACR1) ...................................................... 145
7.3 Operand Cache Operation................................................................................................. 145
7.3.1 Read Operation .................................................................................................... 145
7.3.2 Write Operation ................................................................................................... 146
7.3.3 Write-Back Buffer ............................................................................................... 148
7.3.4 Write-Through Buffer.......................................................................................... 148
7.3.5 RAM Mode .......................................................................................................... 148
7.3.6 OC Index Mode ................................................................................................... 149
7.3.7 Coherency between Cache and External Memory ............................................... 149
7.3.8 Prefetch Operation ............................................................................................... 149
7.4 Instruction Cache Operation ............................................................................................. 150
7.4.1 Read Operation .................................................................................................... 150
7.4.2 IC Index Mode ..................................................................................................... 150
7.5 Memory-Mapped Cache Configuration (Cache Direct Mapping Mode) .......................... 151
7.5.1 IC Address Array ................................................................................................. 151
7.5.2 IC Data Array....................................................................................................... 152
7.5.3 OC Address Array ............................................................................................... 153
7.5.4 OC Data Array ..................................................................................................... 155
7.6 Memory-Mapped Cache Configuration (Double-Size Cache Mode)................................ 156
7.6.1 IC Address Array ................................................................................................. 156
7.6.2 IC Data Array....................................................................................................... 157
7.6.3 OC Address Array ............................................................................................... 158
7.6.4 OC Data Array ..................................................................................................... 160
7.6.5 Summary of Memory-Mapping of OC ................................................................ 161
7.7 Store Queues ..................................................................................................................... 161
7.7.1 SQ Configuration................................................................................................. 161
7.7.2 Writing to SQ....................................................................................................... 162
7.7.3 Transfer to External Memory............................................................................... 162
7.7.4 Determination of SQ Access Exception............................................................... 163
7.7.5 Reading from SQ ................................................................................................. 164
Rev. 1.0, 02/03, page viii of xlviii