SH7760 Datasheet, PDF (586/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Pck
The clock divided
from Pck
input signal
edge detection
Figure 16.2 Edge Detection
The timing diagram in figure 16.2 shows an edge detection (rising edge). The input pin must be
asserted for at least two clock resolution cycles.
16.4.2 32-Bit Timer: Input Capture
When operating in input capture mode, the channel will detect an edge on the input signal. The
selection of rising or falling edge is programmable. When this edge is detected, the current value
of the free-running timer (FRT) is captured into the channel time register for that channel. In
addition, the interrupt edge bit for that channel will be set. In this case, if the interrupt enable bit
for that channel is set, an interrupt will be generated.
Common between channels
Clock generation
CMT_CTR
Edge
detection
32-bit free-running timer
Multiplexer
Peripheral bus
Channel time register
Edge
control
IRQ
Figure 16.3 32-Bit Timer Mode: Input Capture
Rev. 1.0, 02/03, page 536 of 1294