SH7760 Datasheet, PDF (1117/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

5. Packed 2bpp (Pixel Alignment in Byte is Little Endian)
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P03 P02 P01 P00 (Byte0)
+01
P07 P06 P05 P04 (Byte1)
+02
+03
…
…
+LAO+00 P13 P12 P11 P10
+LAO+01 P17 P16 P15 P14
+LAO+02
…
+LAO+03
…
Display Memory
6. Packed 4bpp (Pixel Alignment in Byte is Little Endian)
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P01
P00
(Byte0)
+01
P04
P03
(Byte1)
+02
P06
P05
(Byte2)
+03
…
…
+LAO+00
P11
P10
+LAO+01
P13
P12
+LAO+02
+LAO+03
…
P15
P14
…
Display Memory
7. Unpacked 4bpp [Windows CE Recommended Format]
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P00
(Byte0)
+01
P01
(Byte1)
+02
P02
(Byte2)
+03
…
…
+LAO+00
P10
+LAO+01
P11
+LAO+02
+LAO+03
…
P12
…
Display Memory
8. Unpacked 5bpp [Windows CE Recommended Format]
MSB
LSB
Address
+00
7 6 5 4 3 2 1 0 ^[Bit]
P00
(Byte0)
+01
P01
(Byte1)
+02
P02
(Byte2)
+03
…
…
+LAO+00
P10
+LAO+01
P11
+LAO+02
+LAO+03
…
P12
…
Display Memory
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn = Pn[1:0]: Put 2bit data
LAO: Line Address Offset
—Unused bits should be 0
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn = Pn[3:0]: Put 4bit data
LAO: Line Address Offset
—Unused bits should be 0
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn = Pn[3:0]: Put 4bit data
LAO: Line Address Offset
—Unused bits should be 0
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn = Pn[4:0]: Put 5bit data
LAO: Line Address Offset
—Unused bits should be 0
Rev. 1.0, 02/03, page 1067 of 1294