SH7760 Datasheet, PDF (962/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Register Name
Response register 8
Response register 9
Response register 10
Response register 11
Response register 12
Response register 13
Response register 14
Response register 15
Response register 16
Data timeout register
Data register
FIFO pointer clear register
DMA control register
Interrupt control register 2
Interrupt status register 2
Receive data timing select register
Abbrev. R/W
RSPR8 R/W
RSPR9 R/W
RSPR10 R/W
RSPR11 R/W
RSPR12 R/W
RSPR13 R/W
RSPR14 R/W
RSPR15 R/W
RSPR16 R/W
DTOUTR R/W
DR
R/W
FIFOCLR W
DMACR R/W
INTCR2 R/W
INTSTR2 R/W
RDTIMSEL R/W
P4 Address
H’FE50 0028
H’FE50 0029
H’FE50 002A
H’FE50 002B
H’FE50 002C
H’FE50 002D
H’FE50 002E
H’FE50 002F
H’FE50 0030
H’FE50 0032
H’FE50 0040
H’FE50 0042
H’FE50 0044
H’FE50 0046
H’FE50 0048
H’FE50 004A
Area 7 Address Size
H’1E50 0028 8
H’1E50 0029 8
H’1E50 002A 8
H’1E50 002B 8
H’1E50 002C 8
H’1E50 002D 8
H’1E50 002E 8
H’1E50 002F 8
H’1E50 0030 8
H’1E50 0032 16
H’1E50 0040 16
H’1E50 0042 8
H’1E50 0044 8
H’1E50 0046 8
H’1E50 0048 8
H’1E50 004A 8
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Table 26.2 Register Configuration (2)
Register Name
Command register 0
Command register 1
Command register 2
Command register 3
Command register 4
Command register 5
Command start register
Operation control register
Card status register
Interrupt control register 0
Abbrev.
Power-on Manual Reset
Standby
Reset by by RESET Sleep
by
RESET Pin/WDT/
by Sleep
Software/
Pin/WDT/ Multiple
Instruction/ by
Each
H-UDI Exception Deep Sleep Hardware Module
CMDR0 H’00
H’00
Retained
* Retained
CMDR1 H’00
H’00
Retained
Retained
CMDR2 H’00
H’00
Retained
Retained
CMDR3 H’00
H’00
Retained
Retained
CMDR4 H’00
H’00
Retained
Retained
CMDR5 H’00
H’00
Retained
Retained
CMDSTRT H’00
H’00
Retained
Retained
OPCR H’00
H’00
Retained
Retained
CSTR H’0x
H’0x
Retained
Retained
INTCR0 H’00
H’00
Retained
Retained
Rev. 1.0, 02/03, page 912 of 1294