SH7760 Datasheet, PDF (1077/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Scan Mode Operation: After A/D conversion is performed, the interval for storing the result in
the corresponding data register is fixed at 256 cycles when Pck/8 is selected as the clock division
ratio. Therefore, data is stored in the data registers every 256 cycles.
After an interrupt occurs, data should be read within 256 cycles. After this read, data should be
read at the specified intervals.
Pck
ADDRA write
enable signal
ADDRB write
enable signal
ADDRC write
enable signal
ADDRD write
enable signal
ADDRA
ADDRB
ADDRC
ADDRD
Read signal
(read interval)
ADF
A/D conversion 1
A/D conversion 2
256 clocks
A/D conversion 1'
256 clocks
A/D conversion 2'
A/D conversion 3
A/D conversion 4
256 clocks
A/D conversion 3'
256 clocks
A/D conversion 4'
256 clocks
Read of A/D
conversion 1
Read at intervals of 256 clocks
Read of A/D
conversion 2
Read of A/D
conversion 3
Read of A/D
conversion 4
Read of A/D
conversion 1'
Cycles through all selected channels (AN0 to AN3)
Interrupt signal
ADI Interrupt occurs
Figure 29.5 Timing for Data Write when Four Channels are Selected in Multi Mode
Rev. 1.0, 02/03, page 1027 of 1294