SH7760 Datasheet, PDF (466/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

DREQ
Bus returned to CPU
Bus cycle
CPU
CPU
CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
CPU
Figure 11.10 Example of DMA Transfer in Cycle Steal Mode
• Burst Mode
In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data
continuously until the transfer end condition is satisfied. With DREQ low level detection in
external request mode, however, when DREQ is driven high the bus passes to another bus
master after the end of the DMAC transfer request that has already been accepted, even if the
transfer end condition has not been satisfied.
Figure 11.11 shows an example of DMA transfer timing in burst mode. The following transfer
conditions are used in this example:
• Single address mode
• DREQ level detection (DS = 0 and TM = 1 in CHCRn, external request 2-channel
mode)
Note: Specify DREQ edge detection when performing burst transfer in DMABRG mode.
Operations in burst mode with DREQ level detection in DMABRG mode are the
same as those in cycle steal mode.
DREQ
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 11.11 Example of DMA Transfer in Burst Mode
(3) Relationship between DMA Transfer Type, Request Mode, and Bus Mode
Table 11.8 shows the relationship between the type of DMA transfer, the request mode, and
the bus mode.
Rev. 1.0, 02/03, page 416 of 1294