SH7760 Datasheet, PDF (780/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bits
Bit Name Initial Value R/W Description
3
RD
0
R/W Resume Detected
0: Operation is not affected
1: Interrupt generation due to Resume Detected is
enabled
2
SF
0
R/W Start of Frame
0: Operation is not affected
1: Interrupt generation due to Start of Frame is
enabled
1
WDH
0
R/W Writeback Done Head
0: Operation is not affected
1: Interrupt generation for HcDoneHead Writeback is
enabled
0
SO
0
R/W Scheduling Overrun
0: Operation is not affected
1: Interrupt generation due to Scheduling Overrun is
enabled
21.3.6 Interrupt Disable Register (HcInterruptDisable)
Each disable bit in the HcInterruptDisable corresponds to the related interrupt bit in
HcInterruptStatus. Writing 1 to a bit in the HcInterruptDisable clears the corresponding bit in
HcInterruptEnable to 0. Writing 0 to a bit leaves the corresponding bit in HcInterruptEnable
unchanged. Reading this register will return the current value of HcInterruptEnable.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIE OC ^-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
- RHSC FNO UE RD SF WDH SO
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 730 of 1294