SH7760 Datasheet, PDF (1085/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 30 LCD Controller (LCDC)
A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data
for display is stored in system memory. The LCDC module reads data from system memory, uses
the palette memory to determine the colors, then puts the display on the LCD panel. It is possible
to connect the LCDC to the LCD module of most types other than microcomputer bus interface
types and NTSC/PAL types and those that apply the LVDS interface.
30.1 Features
The LCDC has the following features.
• Panel interface
 Serial interface method
 Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width) *¹
• Supports 4/8/15/16-bpp (bits per pixel) color modes
• Supports 1/2/4/6-bpp grayscale modes
• Supports LCD-panel sizes from 16 × 1 to 1024 × 1024*²
• 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color
control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker.
• Dedicated display memory is unnecessary using part of the SDRAM connected to area 3 of the
CPU as system memory.
• The display is stable because of the large 2.4-kbyte line buffer
• Supports the inversion of the output signal to suit the LCD panel's signal polarity
• Supports the selection of data formats (the endian setting for bytes, backed pixel method) by
register settings
• A hardware-rotation mode is included to support the use of landscape-format LCD panels as
portrait-format LCD panels (the horizontal width of the panel before rotation must be within
320 pixels—see table 30.4).
Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit
lines should be connected to GND or to the lowest bit from which data is output.
2. For details, see section 30.4.1, Size of LCD Modules Which Can Be Displayed with
this LCDC.
Rev. 1.0, 02/03, page 1035 of 1294