SH7760 Datasheet, PDF (453/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
12 to 0 SZ12 to SZ0 All 0
R/W
Description
Transfer Data Size
Specifies the number of bytes to be transferred in
a USB DMA transfer. Up to 8191 bytes can be
specified. Setting these bits as as H’0000
(SZ[12:0]=H’0000) will not perform transfer, but
setting the START bit in DMAUCR to 1 sets the
UTF bit in DMABRGCR to 1.
11.3.20 DMA USB Control Register (DMAUCR)
DMAUCR is a 32-bit readable/writable register that specifies the start of USB DMA transfer
between the shared memory and synchronous DRAM, and the data alignment mode. The setting of
the data alignment mode is also valid for accesses to the USB from the CPU. For details of the
data alignment mode, see section 11.6.13, USB Endian Conversion Function.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
- CVRT1CVRT0
Initial value: 0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
- START -
Initial value: 0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
RR
R
R
R
R
R
R
R R/W R
Bit
Bit Name
31 to 18 
17
CVRT1
16
CVRT0
15 to 2 
Initial Value R/W
All 0
R
0
R/W
0
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Alignment Mode
00: Alignment is not performed
01: Byte boundary mode
10: Longword/word boundary mode
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.0, 02/03, page 403 of 1294