SH7760 Datasheet, PDF (975/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
Initial
Value R/W
4
DATAEN 0
R/W
3 to 0 —
All 0 R
Description
Data Enable
Starts write data transmission by a command with
write data. This bit is cleared automatically when 1 is
written. Resumes transfer clock output and write data
transmission when the transfer clock has been halted
by FIFO empty or termination of one block writing in
multiblock write.
Write enabled period: (1) after receiving a response to
a command with write data, (2) while transfer clock is
halted by FIFO empty, (3) when one block writing in
multiblock write is terminated
Write of 0: Operation is not affected.
Write of 1: Starts or resumes transfer clock output
and write data transmission.
Reserved
These bits are always read as 0. The write value
should always be 0.
Some states of the multimedia card cause command sequence on the multimedia card side to stop.
Table 26.6 shows the card states in which a command sequence is halted. In this case, the
command sequence should also be aborted by setting the CMDOFF bit to 1 on the MMCIF side.
Table 26.6 Card States in which Command Sequence is Halted
Card Operating Mode
MMC mode Command response
Data status
Error Status
When the error detection bit in the card status (32 bits)
in the command response data transmitted by the card
is set.
When the CRCERI bit is set due to an error in the CRC
status to be transmitted from the card is set while block
data is transmitted to the card.
In write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the transfer clock (MCCLK)
output should be temporarily halted by FIFO full/empty, and it should be resumed when the
preparation has been completed.
Rev. 1.0, 02/03, page 925 of 1294