SH7760 Datasheet, PDF (1066/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

29.3 Register Descriptions
The A/D converter has the following registers. For details of register addresses and register states
during each process, see section 32, List of Register.
Table 29.2 Register Configuration (1)
Register Name
Abbrev.
A/D conversion data register A
ADDRA
A/D conversion data register B
ADDRB
A/D conversion data register C
ADDRC
A/D conversion data register D
ADDRD
A/D conversion control/status register ADCSR
R/W P4 Address
R
H’FE28 0000
R
H’FE28 0002
R
H’FE28 0004
R
H’FE28 0006
R/W*² H’FE28 0008
Area 7 Address Size
H’1E28 0000 16
H’1E28 0002 16
H’1E28 0004 16
H’1E28 0006 16
H’1E28 0008 16
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Table 29.2 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
Standby
by RESET Sleep
by
Pin/WDT/ by Sleep
Software/
Multiple
Instruction/ by
Each
Exception Deep Sleep Hardware Module
A/D conversion data register A
ADDRA H’0000 H’0000
Retained
* H’0000*¹
A/D conversion data register B
ADDRB H’0000 H’0000
Retained
H’0000*¹
A/D conversion data register C
ADDRC H’0000 H’0000
Retained
H’0000*¹
A/D conversion data register D
ADDRD H’0000 H’0000
Retained
H’0000*¹
A/D conversion control/status register ADCSR H’0040 H’0040
Retained
H’0040*¹
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the
RESET pin.
*1. Before entering module standby or software standby mode, check that A/D conversion
is not in progress. If standby mode is entered while A/D conversion is in progress,
correct register values are not guaranteed.
*2. Only 0 can be written to bit 15 for clearing the flag.
Rev. 1.0, 02/03, page 1016 of 1294