SH7760 Datasheet, PDF (1053/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 28.3 (7) SDBSR Configuration
Bit Abbreviation
I/O*
Bit Abbreviation
I/O*
130 A23
IN
100 IRL2
IN
129 A23
OUT
99 IRL2
OUT
128 A23
Control 98 IRL2
Control
127 A22
IN
97 IRL3
IN
126 A22
OUT
96 IRL3
OUT
125 A22
Control 95 IRL3
Control
124 CAN1_RX/AUDATA[3]
IN
94 Reserved/AUDATA[1]
IN
123 CAN1_RX/AUDATA[3]
OUT
93 Reserved/AUDATA[1]
OUT
122 CAN1_RX/AUDATA[3]
Control 92 Reserved/AUDATA[1]
Control
121 CAN0_RX/AUDATA[2]
IN
91 ADTRG/AUDATA[0]
IN
120 CAN0_RX/AUDATA[2]
OUT
90 ADTRG/AUDATA[0]
OUT
119 CAN0_RX/AUDATA[2]
Control 89 ADTRG/AUDATA[0]
Control
118 A25
IN
88 Reserved/AUDATA[3]
IN
117 A25
OUT
87 Reserved/AUDATA[3]
OUT
116 A25
Control 86 Reserved/AUDATA[3]
Control
115 A24
IN
85 Reserved/AUDATA[2]
IN
114 A24
OUT
84 Reserved/AUDATA[2]
OUT
113 A24
Control 83 Reserved/AUDATA[2]
Control
112 CAN1_NERR/AUDSYNC
IN
82 Reserved/AUDSYNC
IN
111 CAN1_NERR/AUDSYNC
OUT
81 Reserved/AUDSYNC
OUT
110 CAN1_NERR/AUDSYNC
Control 80 Reserved/AUDSYNC
Control
109 CAN0_NERR/AUDCK
IN
79 Reserved/AUDCK
IN
108 CAN0_NERR/AUDCK
OUT
78 Reserved/AUDCK
OUT
107 CAN0_NERR/AUDCK
Control 77 Reserved/AUDCK
Control
106 IRL0
IN
76 MD8
IN
105 IRL0
OUT
75 MD7
IN
104 IRL0
Control 74 MD7
OUT
103 IRL1
IN
73 MD7
Control
102 IRL1
OUT
72 MD5
IN
101 IRL1
Control 71 MD5
OUT
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven
according to the OUT value.
Rev. 1.0, 02/03, page 1003 of 1294