SH7760 Datasheet, PDF (187/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 7 Caches
7.1 Features
This LSI has an on-chip 16-kbyte instruction cache (IC) for instructions and an on-chip 32-kbyte
operand cache (OC) for data. Half of the memory of the operand cache (16 kbytes) may
alternatively be used as on-chip RAM. When the EMODE bit in CCR is 0, this LSI's cache
behaves as shown in table 7.1. The features of the cache when the EMODE bit in CCR is 1 are
given in table 7.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset.
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. The features of the store queues are given in table 7.3.
Table 7.1 Cache Features (EMODE = 0)
Item
Capacity
Instruction Cache
8-kbyte cache
Type
Line size
Entries
Write method
Direct mapping
32 bytes
256 entires

Operand Cache
16-kbyte cache or
8-kbyte cache + 8-kbyte RAM
Direct mapping
32 bytes
512 entires
Copy-back/write-through selectable
Table 7.2 Cache Features (EMODE = 1)
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Instruction Cache
Operand Cache
16-kbyte cache
32-kbyte cache or
16-kbyte cache + 16-kbyte RAM
2-way set-associative
2-way set-associative
32 bytes
32 bytes
256 entries/way
512 entries/way

Copy-back/write-through selectable
LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Rev. 1.0, 02/03, page 137 of 1294