SH7760 Datasheet, PDF (239/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(8) Unconditional Trap
• Source: Execution of TRAPA instruction
• Transition address: VBR + H'0000 0100
• Transition operations:
As this is a processing-completion-type exception, the PC contents for the instruction
following the TRAPA instruction are saved in SPC. The value of SR and R15 when the
TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the
TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160
is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC =
VBR + H'0100.
TRAPA_exception()
{
SPC = PC + 2;
SSR = SR;
SGR = R15;
TRA = imm << 2;
EXPEVT = H'0000 0160;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
}
Rev. 1.0, 02/03, page 189 of 1294