SH7760 Datasheet, PDF (983/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit Name Value R/W
7 FEI
0
R/W
6 FFI
0
R/W
5 DRPI 0
R/W
4 DTI
0
R/W
Description
FIFO Empty Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading FEI = 1.
1: Interrupt requested
[Setting condition]
When FIFO becomes empty while FEIE = 1 and
data is being transmitted
(when the FIFO_EMPTY bit in CSTR is set)
FIFO Full Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading FFI = 1.
1: Interrupt requested
[Setting condition]
When FIFO becomes full while FFIE = 1 and
data is being received
(when the FIFO_FULL bit in CSTR is set)
Data Response Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading DRPI = 1.
1: Interrupt requested
[Setting condition]
When the CRC status is received while DRPIE
= 1.
Data Transfer End Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading DTI = 1.
1: Interrupt requested
[Setting condition]
When the number of bytes of data transfer
specified in TBCR ends while DTIE = 1.
Interrupt
output
MMCI0
MMCI0
MMCI1
MMCI1
Rev. 1.0, 02/03, page 933 of 1294