SH7760 Datasheet, PDF (314/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

10.5.7 Wait Control Register 3 (WCR3)
WCR3 is a 32-bit readable/writable register that specifies the cycles to be inserted for each area
during the address setup time before the read/write strobe is asserted and during the data-hold time
after the write strobe is negated.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
A6S0 A6H1 A6H0
-
A4
A5S0 A5H1 A5H0 _RDH A4S0 A4H1 A4H0
Initial value: 0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
R/W: R
R
R
R
R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
A3S0 A3H1 A3H0
-
A1
A2S0 A2H1 A2H0 _RDH A1S0 A1H1 A1H0
-
A0S0 A0H1 A0H0
Initial value: 0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
R/W: R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Bit
Initial
Bit
Name Value R/W
31 to 
27, 23,
15, 11,
3
All 0
R
4n + 2 AnS0 All 1
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Area n Write Strobe Setup Time
Specifies the number of cycles to be inserted during the
address setup time before the read/write strobe is
asserted. Valid only for SRAM interface, byte control
SRAM interface, and burst ROM interface:
Cycles to be inserted during the setup time
0: 0
1: 1
Rev. 1.0, 02/03, page 264 of 1294