SH7760 Datasheet, PDF (366/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

issued depending on the bank and row address, but since the write data is output at the same
time as the WRIT command, the PRE, ACTV, and WRIT commands are issued so that one or
two dummy cycles occur automatically on the data bus. Similarly, when a read access follows
a write access, or a write access follows a write access, the PRE, ACTV, or READ command
is issued during the data write cycle for the preceding access. However, a PRE command
cannot be issued for different row addresses in the same bank, and so the PRE command is
issued following the number of Trwl cycles specified by the TRWL bit in MCR after the end
of the last data write cycle.
Figure 10.26 shows a burst read cycle for different banks and row addresses from the
preceding burst read cycle.
Pipelined access is enabled only for consecutive access to area 3, and is aborted when there is
an access to another area. Pipelined access is also aborted in the event of a refresh cycle, or bus
release due to bus arbitration. The cases where pipelined access is available are shown in table
10.16. In this table, DMAC dual indicates transfer by DMAC dual address mode, and DMAC
single indicates transfer by DMAC single address mode.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31-D0
(read)
BS
CKE
Tc1_A
H/L
c1_A
H/L
c5_A
Tc1_B
H/L
c1_B
H/L
c5_B
a1 a2 a3 a4 a5 a6 a7 a8 b1 b2
Figure 10.26 Burst Read Cycle for Different Bank and Row Address From Preceding Burst
Read Cycle
Rev. 1.0, 02/03, page 316 of 1294