SH7760 Datasheet, PDF (774/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

21.3.3 Command Status Register (HcCommandStatus)
HcCommandStatus indicates the current status of HC. HC reads this register to receive a
command issued by HCD. HCD sets each bit by writing 1 and HC clears it by writing 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
- SOC1 SOC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
- OCR BLF CLF HCR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bits
31 to
18
17
16
15 to 4
3
Bit Name

SOC1
SOC0

OCR
Initial Value R/W
All 0
R
0
R
0
R
All 0
R
0
R/W
Description
Reserved
These bits are always read as 0. Always write 0 to
these bits.
Scheduling Overrun Count
These bits are incremented in each
SchedulingOverrun error. These bits are initialized to
B′00 and wrap around at B’11. These bits are
incremented when scheduling overrun is detected
even though the SO bit in HcInterruptStatus is set.
These bits are used by HCD to monitor any
persistent scheduling problem.
Reserved
These bits are always read as 0. Always write 0 to
these bits.
Ownership Change Request
This bit is set to 1 by OS HCD to request a change of
control of HC. When this bit is1, HC sets the OC bit
in the HcInterruptStatus. After a change, this bit is
cleared to 0 and remains 0 until the next request
from OS HCD.
0: Do not request the change of the control of HC
1: Request the change of the control of HC
Rev. 1.0, 02/03, page 724 of 1294