SH7760 Datasheet, PDF (318/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W
Description
21
TPC2 0
20
TPC1 0
19
TPC0 0
R/W RAS Precharge Period
R/W
When synchronous DRAM interface is in use, these bits
R/W
specify the minimum number of cycles until the next
bank active command is issued after precharging.
RAS Precharge Time (SDRAM)
000: 1*¹
001: 2
010: 3
011: 4*¹
100: 5*¹
101: 6*¹
110: 7*¹
111: 8*¹
18

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
17
RCD1 0
16
RCD0 0
R/W RAS-CAS Delay
R/W
When using the synchronous DRAM interface, specify
ACTIVE to READ or WRITE delay in these bits.
00: Setting prohibited
01: 2 cycles
10: 3 cycles
11: 4 cycles*¹
Rev. 1.0, 02/03, page 268 of 1294