SH7760 Datasheet, PDF (431/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 11.4 DMABRG Mode (DMS[1:0] in DMAOR = 11)
Bit 11: Bit 10: Bit 9:
RS3 RS2 RS1
0
0
0
Bit 8:
RS0
0
Description
External request*¹*²
Dual address mode
External address space → external address space
1
Setting prohibited
1
0
External request*¹*², DMABRG request*²*³
Single address mode*⁴, External address space → external
device
1
External request*¹*², DMABRG request*²*³
Single address mode*⁴, External device → external address
space
1
0
0
Auto-request (external address space → external address
space)
1
Auto-request (external address space → on-chip peripheral
module)
1
0
Auto-request (on-chip peripheral module → external address
space)
1
On-chip peripheral module request*²*⁵
External address space → on-chip peripheral module
1
0
0
0
Setting prohibited
1
Setting prohibited
1
0
Setting prohibited
1
Setting prohibited
1
0
0
TMU channel 2 (input capture interrupt)
External address space → external address space
1
TMU channel 2 (input capture interrupt)
External address space → on-chip peripheral module
1
0
TMU channel 2 (input capture interrupt)
On-chip peripheral module → external address space
1
On-chip peripheral module request*²*⁵
On-chip peripheral module → external address space
Notes: *1. External requests can be accepted in all channels. DREQ0 to DREQ3 can be used.
Note that the DREQ pin number and channel number do not match.
*2. DMARSRA and DMARSRB values should be specified in addition to setting this bit.
*3. DMABRG requests can only be accepted in channel 0. A DMABRG request is a
transfer request from the LCDC, HAC(0)/(1), SSI(0)/(1), and USB. This bit is
automatically set when a DMABRG request is issued.
*4. Only single address mode for synchronous DRAM can be set.
*5. On-chip peripheral modules except for LCDC, HAC, SSI, USB, and TMU.
Rev. 1.0, 02/03, page 381 of 1294