SH7760 Datasheet, PDF (648/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(3) Break Detection and Processing
If a framing error (FER) is detected, break signals can also be detected by reading the
SCIF_RXD pin value directly. In the break state the input from the SCIF_RXD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the
receive operation continues.
(4) Sending a Break Signal
The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and
SPB2DT in SCSPTR. This feature can be used to send a break signal.
After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission),
the SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the
mark state. The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and
high level) in the beginning.
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), and then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized, regardless of the current transmission state, and 0 is output from the
SCIF_TXD pin.
(5) Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the bit
rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the eighth base clock pulse.
The timing is shown in figure 17.22.
Rev. 1.0, 02/03, page 598 of 1294