SH7760 Datasheet, PDF (492/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(1) Conditions for Ending Transfer on Individual Channels
Transfer ends on the corresponding channel when either of the following conditions is satisfied:
• The DMATCR value reaches 0.
• The DE bit in CHCR is cleared to 0.
1. End of transfer when DMATCR = 0
When the DMATCR value reaches 0, the DMAC terminates DMA transfer on the
corresponding channel and sets the TE bit in CHCR. If the IE bit is set at this time, an interrupt
(DMTE) request is sent to the CPU (an interrupt (DMTE) request can not be sent to the CPU
for a DMA transfer end when DMATCR = 0 in a DMABRG request).
Transfer ending with DMATCR = 0 does not follow the procedures described in 1, 2, 3, and 4
in section 11.4.6.
2. End of transfer when DE = 0 in CHCR
When the DE bit in CHCR is cleared to 0, DMA transfer is suspended on the corresponding
channel. (During a DMA transfer in a DMABRG request, do not clear the DE bit to 0 by
accessing from the CPU.) The TE bit is not set in this case. Transfer ending in this case follows
the procedures described in 1, 2, 3, and 4 in section 11.4.6.
(2) Conditions for Ending Transfer Simultaneously on All Channels
Transfer ends on all channels simultaneously when either of the following conditions is
satisfied:
• The AE or NMIF bit in DMAOR is set to 1.
• The DME bit in DMAOR is cleared to 0.
1. End of transfer with DMAOR.AE = 1
If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all
channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is
passed to the CPU. Therefore, when the AE bit is set to 1, SAR, DAR, and DMATCR values
indicate the addresses for the DMA transfer to be performed next and the remaining number of
transfers. The TE bit is not set to 1 in this case. To resume DMA transfer, first correct the
channel settings that caused the address error. Next re-specify DMARSRA/DMARSRB even if
there is no change in resource. After that read AE = 1 and then write AE = 0. Acceptance of
external requests is suspended while the AE bit is set to 1, so a DMA transfer request must be
reissued when resuming transfer. Acceptance of on-chip peripheral module requests is also
suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-
chip peripheral module must be cleared to 0 before the new setting is made. DMABRG must
be reset for DMABRG requests. See section 11.6.2, DMABRG Reset for the procedure.
Rev. 1.0, 02/03, page 442 of 1294