SH7760 Datasheet, PDF (963/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Register Name
Abbrev.
Power-on Manual Reset
Standby
Reset by by RESET Sleep
by
RESET Pin/WDT/
by Sleep
Software/
Pin/WDT/ Multiple
Instruction/ by
Each
H-UDI Exception Deep Sleep Hardware Module
Interrupt control register 1
INTCR1 H’00
H’00
Retained
* Retained
Interrupt status register 0
INTSTR0 H’00
H’00
Retained
Retained
Interrupt status register 1
INTSTR1 H’00
H’00
Retained
Retained
Transfer clock control register
CLKON H’00
H’00
Retained
Retained
Command timeout control register CTOCR H’00
H’00
Retained
Retained
Transfer byte number count register TBCR H’00
H’00
Retained
Retained
Mode register
MODER H’00
H’00
Retained
Retained
Command type register
CMDTYR H’00
H’00
Retained
Retained
Response type register
RSPTYR H’00
H’00
Retained
Retained
Response register 0
RSPR0 H’00
H’00
Retained
Retained
Response register 1
RSPR1 H’00
H’00
Retained
Retained
Response register 2
RSPR2 H’00
H’00
Retained
Retained
Response register 3
RSPR3 H’00
H’00
Retained
Retained
Response register 4
RSPR4 H’00
H’00
Retained
Retained
Response register 5
RSPR5 H’00
H’00
Retained
Retained
Response register 6
RSPR6 H’00
H’00
Retained
Retained
Response register 7
RSPR7 H’00
H’00
Retained
Retained
Response register 8
RSPR8 H’00
H’00
Retained
Retained
Response register 9
RSPR9 H’00
H’00
Retained
Retained
Response register 10
RSPR10 H’00
H’00
Retained
Retained
Response register 11
RSPR11 H’00
H’00
Retained
Retained
Response register 12
RSPR12 H’00
H’00
Retained
Retained
Response register 13
RSPR13 H’00
H’00
Retained
Retained
Response register 14
RSPR14 H’00
H’00
Retained
Retained
Response register 15
RSPR15 H’00
H’00
Retained
Retained
Response register 16
RSPR16 H’00
H’00
Retained
Retained
Data timeout register
DTOUTR H’FFFF H’FFFF
Retained
Retained
Data register
DR
H’xxxx H’xxxx
Retained
Retained
FIFO pointer clear register
FIFOCLR H’00
H’00
Retained
Retained
DMA control register
DMACR H’00
H’00
Retained
Retained
Rev. 1.0, 02/03, page 913 of 1294