SH7760 Datasheet, PDF (944/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
31 to 23 
Initial Value R/W
All 0
R
22
STARYIE 0
R/W
21
STDRYIE 0
R/W
20
PLRFRQIE 0
R/W
19
PRRFRQIE 0
R/W
18 to 14 
All 0
R
13
PLRFOVIE 0
R/W
12
PRRFOVIE 0
R/W
11 to 0 
All 0
R
Description
Reserved
Always 0 for read and write.
Status Address Ready Interrupt Enable
0: Disables status address ready interrupts.
1: Enables status address ready interrupts.
Status Data Ready Interrupt Enable
0: Disables status data ready interrupts.
1: Enables status data ready interrupts.
PCML RX Request Interrupt Enable
0: Disables PCML RX request interrupts.
1: Enables PCML RX request interrupts.
PCMR RX Request Interrupt Enable
0: Disables PCMR RX request interrupts.
1: Enables PCMR RX request interrupts.
Reserved
Always 0 for read and write.
PCML RX Overrun Interrupt Enable
0: Disables PCML RX overrun interrupts.
1: Enables PCML RX overrun interrupts.
PCMR RX Overrun Interrupt Enable
0: Disables PCMR RX overrun interrupts.
1: Enables PCMR RX overrun interrupts.
Reserved
Always 0 for read and write.
Rev. 1.0, 02/03, page 894 of 1294