SH7760 Datasheet, PDF (328/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

10.5.13 Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable counter that is incremented by the input clock (selected by
bits CKS2 to CKS0 in RTCSR). When the RTCNT value matches the RTCOR value, the CMF bit
is set in RTCSR and the RTCNT value is cleared.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: -
-
-
-
-
-
-
8
7
6
5
4
3
2
1
0
-
0
0
0
0
0
0
0
0
0
- R/W R/W R/W R/W R/W R/W R/W R/W
10.5.14 Refresh Time Constant Register (RTCOR)
RTCOR is a readable/writable register that specifies the upper limit of RTCNT. The RTCOR and
RTCNT values (lower 8 bits) are constantly compared, and when they match, the CMF bit is set in
RTCSR and the RTCNT value is cleared to 0. If the RFSH bit in MCR has been set to 1 and auto-
refresh has been selected as the refresh mode, a memory refresh cycle is generated when the CMF
bit is set.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: -
-
-
-
-
-
-
8
7
6
5
4
3
2
1
0
-
0
0
0
0
0
0
0
0
0
- R/W R/W R/W R/W R/W R/W R/W R/W
10.5.15 Refresh Count Register (RFCR)
RFCR is a 10-bit readable/writable counter that counts the number of refresh cycles by being
incremented each time the RTCOR and RTCNT values match. If the RFCR value exceeds the
count limit specified by the LMTS bit in RTCSR, the OVF bit in RTCSR is set and the RFCR
value is cleared.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: -
-
-
-
-
- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 278 of 1294