SH7760 Datasheet, PDF (1069/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit Name Value R/W
13 ADST 0
R/W
12 DMASL 0
R/W
Description
A/D Start
Starts or stops A/D conversion. This bit remains set to 1
during A/D conversion. It can also be set to 1 by external
trigger input (ADTRG) pin.
0: A/D conversion is stopped
1:
• Single mode: A/D conversion starts. This bit is cleared
to 0 automatically when conversion on the specified
channel ends. Even when the ADST bit is cleared to 0
(by software), A/D conversion does not stop (0 cannot
be written to this bit during A/D conversion).
• Multi mode: A/D conversion starts. This bit is cleared
to 0 automatically when conversion on the specified
channels has been performed for one cycle. When
the ADST bit is cleared to 0 (by software), A/D
conversion stops when the currently executed
channel ends.
• Scan mode: A/D conversion starts. A/D conversion
continues without a break until the ADST bit is cleared
to 0 by software or until all registers are initialized by
a power-on or manual reset or in hardware standby,
module standby, or software standby mode. For the
standby modes, refer to section 29.7.4, Notes on
Standby Modes.
DMAC Select
Selects an interrupt or activation of the DMAC due to the
end of A/D conversion. Do not change the DMASL bit
setting during A/D conversion.
0: An interrupt by the end of A/D conversion is selected
1: Activation of the DMAC by the end of A/D conversion is
selected
Rev. 1.0, 02/03, page 1019 of 1294