SH7760 Datasheet, PDF (193/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
10, 9
Bit Name

8
ICE
7
OIX
6

5
ORA
4

3
OCI
2
CB
Initial Value R/W
All 0
R
0
R/W
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
IC Enable Bit
Selects whether the IC is used. Note however
when address translation is performed, the IC
cannot be used unless the C bit in the page
management information is also 1.
0: IC not used
1: IC used
OC Index Enable Bit
0: Effective address bits [13:5] used for OC entry
selection
1: Effective address bits [25] and [12:5] used for
OC entry selection
When the ORA bit is 1, this bit should be cleared
to 0.
Reserved
This bit is always read as 0. The write value
should always be 0.
OCRAM Bit
When the OC is enabled (OCE = 1), this bit
specifies whether half of the OC is to be used as
RAM. When the OC is disabled (OCE = 0), this
bit should be cleared to 0.
0: Normal mode (the entire OC is used as a
cache)
1: RAM mode (half of the OC is used as a cache
and the other half is used as RAM)
When the OIX bit is 1, this bit should be cleared
to 0.
Reserved
This bit is always read as 0. The write value
should always be 0.
OC Invalidation Bit
When 1 is written to this bit, the V and U bits of
all OC entries are cleared to 0. This bit is always
read as 0.
Copy-Back Bit
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
Rev. 1.0, 02/03, page 143 of 1294