SH7760 Datasheet, PDF (952/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

25.5.6 Initialization Sequence
Figure 25.3 shows an example of the initialization sequence.
START
HAC Cold reset (HACCR = H'0000 0A00)
Start transfer
(HACCR=H'0000220)
HAC
module
initialization
Enable TX/RX
(e.g.: Set HACACR to H'85E0 0000; 20-bit DMA,
TX slots 1 & 2 atomic control)
Codec ready?
No
(HACCR = H'0000 8200)
Yes
Set DMAC
*
Set read address to #h'26.
(HACCSAR = H'000A 6000)
External
codec
device
initialization
Off-chip codec internal status
ADC, DAC, Analog, REF = ready?
No
(HACCSDR = H'0000 00F0)
Yes
Set read volume and sampling rate
(1) HACTSR = H'0000 0000
(2) Set HACCSAR and HACCSDR
Start DMA transfer (Receiver/Transmitter)
Note: * Refer to section 11, Direct Memory Access Controller (DMAC).
Figure 25.3 Initialization Sequence
Rev. 1.0, 02/03, page 902 of 1294