SH7760 Datasheet, PDF (758/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

reset
Module
configration
(after reset)
EN = 0
(IDST = 1)
EN = 1
(IDST = 0)
Module
disabled
(waiting until
bus inactive)
EN = 0
(IDST = 0)
Module
enabled
(normal tx/rx)
Figure 20.20 Transition Diagram between Operation Modes
(1) Configuration Mode
This mode is entered after the module is released from reset. All required settings in the
control register should be defined in this mode, before the SSI module is enabled by setting the
EN bit.
Setting the EN bit causes the SSI module to enter the module enabled mode.
(2) Module Enabled Mode
Operation of the module in this mode depends on the selected operating mode. For details, see
section 20.4.5, Transmit Operation and section 20.4.6, Receive Operation.
20.4.5 Transmit Operation
Transmission can be controlled in one of two ways: either DMA or an interrupt driven.
DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or
overflow of data or DMAC transfer end is notified by using an interrupt.
The alternative is using the interrupts that the SSI module generates to supply data as required.
This mode has a higher interrupt load as the SSI module is only double buffered and will require
data to be written at least every system word period.
When the SSI module has been enabled for transmission, at least one longword must be written to
the transmit register before disabling the transmitter (In 16-bit mode, two 16-bit words will be
transmitted; in 8-bit mode, 4 bytes will be transmitted. For all other data sizes, one data word will
be transmitted, e.g., 18 bits for 18-bit mode.)
Failure to do this will result in a lockup, which requires a power-on or manual reset.
Rev. 1.0, 02/03, page 708 of 1294