SH7760 Datasheet, PDF (701/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Note: * This bit can be written or read. When 0 is written to, the bit is initialized. When 1 is written to,
it is ignored.
19.3.7 Master Interrupt Enable Register (ICMIER)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
- MNRE MALE MSTE MDEE MDTE MDRE MATE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 7 
Initial Value R/W
All 0
R
6
MNRE
0
R/W
5
MALE
0
R/W
4
MSTE
0
R/W
3
MDEE
0
R/W
2
MDTE
0
R/W
1
MDRE
0
R/W
0
MATE
0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Master NACK Received Interrupt Enable
0: The MNR interrupt is disabled
1: The MNR interrupt is enabled
Master Arbitration Lost Interrupt Enable
0: The MAL interrupt is disabled
1: The MAL interrupt is enabled
Master Stop Transmission Interrupt Enable
0: The MST interrupt is disabled
1: The MST interrupt is enabled
Master Data Empty Interrupt Enable
0: The MDE interrupt is disabled
1: The MDE interrupt is enabled
Master Data Transmission Interrupt Enable
0: The MDT interrupt is disabled
1: The MDT interrupt is enabled
Master Data Receive Interrupt Enable
0: The MDR interrupt is disabled
1: The MDR interrupt is enabled
Master Address Transmission Interrupt Enable
0: The MAT interrupt is disabled
1: The MAT interrupt is enabled
Rev. 1.0, 02/03, page 651 of 1294