SH7760 Datasheet, PDF (739/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
7
BREN
0
R/W
6 to 4 CKDV
All 0
R/W
3
MUEN
0
R/W
2
CPEN
0
R/W
1
TRMD
0
R/W
0
EN
0
R/W
Description
Burst Mode Enable
0: Burst mode is disabled.
1: Burst mode is enabled.
Burst mode is used in conjunction with
compressed mode (CPEN = 1). When burst mode
is enabled the SSI_SCK signal is gated. Clock
pulses are output only when there is valid serial
data being output on SSI_SDATA.
Serial Oversampling Clock Division Ratio
These bits define the division ratio between
oversampling Clock (HAC_BIT_CLK) and the
serial bit clock.
These bits are ignored if SCKD = 0.
The Serial Bit Clock is used for the shift register
and is provided on the SSI_SCK pin.
000: (Serial bit clock frequency = oversampling
clock frequency/1)
001: (Serial bit clock frequency = oversampling
clock frequency/2)
010: (Serial bit clock frequency = oversampling
clock frequency/4)
011: (Serial bit clock frequency = oversampling
clock frequency/8)
100: (Serial bit clock frequency = oversampling
clock frequency/16)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Mute Enable
When in transmit mode (TRMD = 1), by making
MUEN = 1, the output of SSI_SDATA will be in
low level.
0: The SSI module is not muted.
1: The SSI module is muted.
Compressed Mode Enable
0: Compressed mode disabled
1: Compressed mode enabled
Transmit/Receive Mode Select
0: The SSI module is in receive mode
1: The SSI module is in transmit mode
SSI Module Enable
0: The SSI module is disabled
1: The SSI module is enabled
Rev. 1.0, 02/03, page 689 of 1294