SH7760 Datasheet, PDF (41/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 33.31 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst
(RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) ..............................................1223
Figure 33.32 Synchronous DRAM Normal Write Bus Cycle:
ACT+WRITE Commands, Burst (RCD[1:0]=01, TRWL[2:0]=010)..................1224
Figure 33.33 Synchronous DRAM Normal Write Bus Cycle:
PRE+ACT+WRITE Commands, Burst
(RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) ..............................................1225
Figure 33.34 Synchronous DRAM Normal Write Bus Cycle:
WRITE Command, Burst (TRWL[2:0]=010)......................................................1226
Figure 33.35 Synchronous DRAM Bus Cycle: Precharge Command (TPC[2:0]=001) ...........1227
Figure 33.36 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS=1, TRC[2:0]=001) ......1228
Figure 33.37 Synchronous DRAM Bus Cycle: Self-Refresh (TRC[2:0]=001) ........................1229
Figure 33.38 Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) ......................1230
Figure 33.39 Synchronous DRAM Bus Cycle: Mode Register Setting (SET) .........................1231
Figure 33.40 PCMCIA Memory Bus Cycle..............................................................................1232
Figure 33.41 PCMCIA I/O Bus Cycle ......................................................................................1233
Figure 33.42 PCMCIA I/O Bus Cycle (TED=1, TEH=1, One Internal Wait, Bus Sizing).......1234
Figure 33.43 MPX Basic Bus Cycle: Read...............................................................................1235
Figure 33.44 MPX Basic Bus Cycle: Write..............................................................................1236
Figure 33.45 MPX Bus Cycle: Burst Read ...............................................................................1237
Figure 33.46 MPX Bus Cycle: Burst Write ..............................................................................1238
Figure 33.47 Memory Byte Control SRAM Bus Cycle ............................................................1239
Figure 33.48 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .......................1240
Figure 33.49 NMI Input Timing ...............................................................................................1241
Figure 33.50 DREQ/DRAK Timing .........................................................................................1242
Figure 33.51 TCLK Input Timing ............................................................................................1242
Figure 33.52 SCIFn_CLK Input Clock Timing ........................................................................1243
Figure 33.53 SCIF I/O Synchronous Mode Clock Timing .......................................................1243
Figure 33.54 TCK Input Timing...............................................................................................1244
Figure 33.55 RESET Hold Timing ...........................................................................................1244
Figure 33.56 H-UDI Data Transfer Timing ..............................................................................1245
Figure 33.57 Pin Break Timing ................................................................................................1245
Figure 33.58 CMT Timing (1) ..................................................................................................1246
Figure 33.59 CMT Timing (2) ..................................................................................................1246
Figure 33.60 HCAN2 Timing ...................................................................................................1247
Figure 33.61 GPIO Timing .......................................................................................................1247
Figure 33.62 Block Diagram of I²C I/O Buffer ........................................................................1248
Figure 33.63 I²C Bus Interface Module Signal Timing ............................................................1250
Figure 33.64 HSPI Data Output/Input Timing..........................................................................1251
Figure 33.65 Input Voltage (V_IH, V_IL) ......................................................................................1252
Figure 33.66 Output (V_OH, V_OL) ...............................................................................................1252
Rev. 1.0, 02/03, page xxxix of xlviii