SH7760 Datasheet, PDF (601/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Ch. Register Name
Abbrev.
Power-on Manual Reset
Standby
Reset by by RESET Sleep
by
RESET Pin/WDT/ by Sleep
Software/
Pin/WDT/ Multiple
Instruction/ by
Each
H-UDI Exception Deep Sleep Hardware Module
0 Serial error register 0
SCRER0 H’0000 H’0000
Retained
* Retained
1 Serial mode register 1
SCSMR1 H’0000 H’0000
Retained
Retained
Bit rate register 1
SCBRR1 H’FF
H’FF
Retained
Retained
Serial control register 1
SCSCR1 H’0000 H’0000
Retained
Retained
Transmit FIFO data register 1 SCFTDR1 Undefined Undefined Retained
Retained
Serial status register 1
SCFSR1 H’0060 H’0060
Retained
Retained
Receive FIFO data register 1 SCFRDR1 Undefined Undefined Retained
Retained
FIFO control register 1
SCFCR1 H’0000 H’0000
Retained
Retained
Transmit FIFO data count
register 1
SCTFDR1 H’0000 H’0000
Retained
Retained
Receive FIFO data count
register 1
SCRFDR1 H’0000 H’0000
Retained
Retained
Serial port register 1
SCSPTR1 H’0000*³ H’0000*³
Retained
Retained
Line status register 1
SCLSR1 H’0000 H’0000
Retained
Retained
Serial error register 1
SCRER1 H’0000 H’0000
Retained
Retained
2 Serial mode register 2
SCSMR2 H’0000 H’0000
Retained
Retained
Bit rate register 2
SCBRR2 H’FF
H’FF
Retained
Retained
Serial control register 2
SCSCR2 H’0000 H’0000
Retained
Retained
Transmit FIFO data register 2 SCFTDR2 Undefined Undefined Retained
Retained
Serial status register 2
SCFSR2 H’0060 H’0060
Retained
Retained
Receive FIFO data register 2 SCFRDR2 Undefined Undefined Retained
Retained
FIFO control register 2
SCFCR2 H’0000 H’0000
Retained
Retained
Transmit FIFO data count
register 2
SCTFDR2 H’0000 H’0000
Retained
Retained
Receive FIFO data count
register 2
SCRFDR2 H’0000 H’0000
Retained
Retained
Serial port register 2
SCSPTR2 H’0000*³ H’0000*³
Retained
Retained
Line status register 2
SCLSR2 H’0000 H’0000
Retained
Retained
Serial error register 2
SCRER2 H’0000 H’0000
Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused
by the RESET pin.
*1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0.
*2. Bits 2 and 0 are undefined.
*3. Bits 6, 4, 2,and 0 are undefined.
*4. To clear the flag, 0 can only be written to bit 0.
Rev. 1.0, 02/03, page 551 of 1294