SH7760 Datasheet, PDF (253/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 9 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to handle interrupt requests according to user-set priority.
9.1 Features
The INTC has the following features.
• Fifteen interrupt priority levels can be set
By setting the eight interrupt priority level setting registers, the priorities of peripheral module
interrupts can be selected from 15 levels for different request sources.
• NMI noise canceler function
The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading
this bit in the interrupt exception handling routine, enabling it to be used as a noise canceler.
• NMI request masking when the BL bit in SR is set to 1.
It is possible to select whether or not NMI requests are to be masked when the BL bit in SR is
set to 1.
Rev. 1.0, 02/03, page 203 of 1294