SH7760 Datasheet, PDF (258/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 9.3 Interrupt Request Sources and IPRA to IPRD
Bits
Register
15 to 12
11 to 8
7 to 4
3 to 0
IPRA
IPRB
IPRC
TMU0
WDT
GPIO (IRL, IRQ)*³
TMU1
REF*¹
DMAC
TMU2
Reserved*²
Reserved*²
Reserved*²
Reserved*²
H-UDI
IPRD
IRL0
IRL1
IRL2
IRL3
Notes: 1. REF is the memory refresh control unit in the bus state controller (BSC). See section 10,
Bus State Controller (BSC), for details.
2. Reserved: These bits are always read as 0. The write value should always be 0.
3. These bits set the interrupt priority level of the GPIO in normal mode and that of the
GPIO, IRL, IRQ4, and IRQ5 in software standby mode. To exit software standby mode
by an IRQ4 or IRQ5 interrupt, INTPRI00 must also be set. The same value must be set
in both registers. Note that software standby mode cannot be exited by an IRQ6 or
IRQ7 interrupt.
As shown in table 9.3, four peripheral modules are assigned to each register. Setting a value from
H'F (1111) to H'0 (0000) in each of the 4-bit groups, 15 to 12, 11 to 8, 7 to 4, and 3 to 0,
configures interrupt priority level for each group. Setting H'F designates priority level 15 (the
highest level), and setting H'0 designates priority level 0 (requests are masked).
9.3.2 Interrupt Priority Level Setting Registers 00 to 0C (INTPRI00 to INTPRI0C)
INTPRI00 to INTPRI0C are 32-bit readable/writable registers that set priority levels from 15 to 0
for the peripheral module interrupts.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 0
Initial Value R/W
All 0
R/W
Description
These bits set the priority level for each interrupt
source in 4-bit units. For details, see table 9.4,
Interrupt Request Sources and INTPRI00 to
INTPRI0C.
Rev. 1.0, 02/03, page 208 of 1294