SH7760 Datasheet, PDF (549/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) Exit from Module Standby Function
In the case of STBCR and STBCR2, the module standby function is exited by writing 0 to the
MSTP6 to MSTP4 and MSTP2 bits. In the case of CLKSTP00, the module standby function is
exited by writing 1 to the corresponding bit in CLKSTPCLR00.
The module standby function is also exited by means of a power-on reset via the RESET pin or
a power-on reset caused by watchdog timer overflow.
14.3.5 Hardware Standby Mode
(1) Transition to Hardware Standby Mode
Setting the CA pin level low effects a transition to hardware standby mode. Note that the CA
pin must be continuously held low while in hardware standby mode. In this mode, all modules
stop, as in software standby mode selected using the SLEEP instruction.
Hardware standby mode differs from software standby mode in the following points:
(a) Interrupts and manual resets are not available.
(b) All output pins other than the STATUS pins are in the high-impedance state and the pull-up
resistance is off.
Operation when a low-level is input to the CA pin in software standby mode depends on the
CPG status, as follows:
(a) In software standby mode
The clock remains stopped and a transition is made to the hardware standby state.
(b) When WDT is operating at the time software standby mode is exited by interrupt
After software standby mode is momentarily exited and the CPU restarts operation, a
transition is made to hardware standby mode.
(2) Exit from Hardware Standby Mode
Hardware standby mode is exited by means of a power-on reset via the RESET pin.
14.3.6 STATUS Pin Change Timing
The timing of STATUS1 and STATUS0 pin changes is shown below.
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